Processing methods of forming an electrically conductive plug to a node location

ABSTRACT

Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location. According to a preferred aspect of the invention, a plurality of insulated conductive lines are formed over a substrate. At least some of the conductive lines constitute word lines and at least some of the conductive lines constitute bit lines. The lines are preferably formed to define and laterally surround an active area substrate location. The substrate location is preferably surrounded by at least four of the lines. Conductive material is deposited over the substrate and the conductive lines and in electrical contact with the node location. The conductive material is then removed to a degree sufficient to form an isolated plug of conductive material over the node location and between the four conductive lines.

TECHNICAL FIELD

[0001] This invention concerns processing methods of forming anelectrically conductive plug to a node location. This invention alsoconcerns methods of forming an electrical connection with an integratedcircuit memory cell node location.

BACKGROUND OF THE INVENTION

[0002] Fabrication of integrated circuitry typically involves formingelectrical connections to substrate node locations. In the context ofintegrated circuit memory devices, such as dynamic random access memorydevices, such electrical connections include those which are made to andbetween storage capacitors and substrate diffusion regions.

[0003] In the past, there have been at least two ways to make suchelectrical connections. A first way of forming such electricalconnections involves depositing a thick insulator material, such asborophosphosilicate glass, over the substrate and then conducting aself-aligned etch thereof to form a contact opening. The contactopening, or at least a portion thereof, is subsequently filled withconductive material. As aspect ratios of such contact openings increase,it becomes more challenging to form such openings and electricalconnections. A second way of forming such electrical connectionsinvolves depositing a conductive material over the entire substrate,patterning and etching such material to define desired electricalconnections, and subsequently forming an insulating dielectric layerover the substrate. Contact openings can then be etched through thedielectric layer. Again, challenges are posed with respect to etchingthe contact openings through the dielectric layer.

[0004] This invention grew out of concerns associated with improving themanner in which electrical connections are made to or with integratedcircuit substrate node locations. This invention also grew out ofconcerns associated with improving the manner in which electricalconnections are made with integrated circuit memory cell node locations.

SUMMARY OF THE INVENTION

[0005] Methods of forming electrical connections with an integratedcircuit substrate node location are described. According to one aspectof the invention, a substrate node location is laterally surrounded withinsulating material and left outwardly exposed. Conductive material isdeposited over the exposed node location. Subsequently, a photomasklessetch of the conductive material is conducted to a degree sufficient toleave a plug of conductive material over the node location. In apreferred implementation, the insulating material with which such nodelocation is surrounded constitutes insulating material portions whichare provided relative to conductive lines which are formed over thesubstrate. In another preferred implementation, such conductive linesform a grid of insulating material which, in turn, defines the nodelocation. According to a preferred aspect of the invention, a pluralityof insulated conductive lines are formed over a substrate. At least someof the conductive lines constitute word lines and at least some of theconductive lines constitute bit lines. The lines are preferably formedto define and laterally surround an active area substrate location. Thesubstrate location is preferably surrounded by at least four of thelines. Conductive material is deposited over the substrate and theconductive lines and in electrical contact with the node location. Theconductive material is then removed to a degree sufficient to form anisolated plug of conductive material over the node location and betweenthe four conductive lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0007]FIG. 1 is a top plan view of a semiconductor wafer fragment at oneprocessing step in accordance with the invention.

[0008]FIG. 2 is a view of the FIG. 1 wafer fragment taken along line 2-2in FIG. 1.

[0009]FIG. 3 is a view of the FIG. 1 wafer fragment taken along line 3-3in FIG. 1.

[0010]FIG. 4 is a view of a portion of the FIG. 1 wafer fragment at aprocessing step subsequent to that shown by FIG. 1.

[0011]FIG. 5 is a view of the FIG. 4 wafer fragment taken along line 5-5in FIG. 4.

[0012]FIG. 6 is a view of the FIG. 4 wafer fragment at a processing stepsubsequent to that shown by FIG. 4.

[0013]FIG. 7 is a view of a portion of the FIG. 6 wafer fragment takenalong line 7-7 in FIG. 6.

[0014]FIG. 8 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 7.

[0015]FIG. 9 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 8.

[0016]FIG. 10 is a view of the FIG. 7 wafer fragment at a processingstep subsequent to that shown by FIG. 9.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0018] Referring to FIG. 1, a semiconductor wafer fragment is showngenerally at 10 and comprises a semiconductive substrate 12. In thecontext of this document, the term “semiconductive substrate” is definedto mean any construction comprising semiconductive material, including,but not limited to bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above. In the preferred embodiment,substrate 12 comprises an integrated circuit memory array area and aperipheral area. For purposes of the discussion herein, only a portionof the memory array area is shown.

[0019] A plurality of isolation oxide runners 14 are formed withinsubstrate 12. One method of forming such runners is by trench and refilltechniques in which substrate portions are etched away and back-filledwith isolation oxide. Subsequent planarization provides the illustratedisolation oxide runners. Respective pairs of runners such as pairs 16define continuous active areas or regions therebetween, such asrespective active areas or regions 18. Active areas or regions 18constitute continuous active areas which are formed within or relativeto substrate 12. A plurality of laterally spaced apart insulativeconductive lines 20, 22, 24, and 26, at least some of which are wordlines, are formed over substrate 12 and disposed generally transverseindividual isolation oxide runners 14. The illustrated conductive linesare formed, in the preferred embodiment, to have respective insulativeor insulating sidewall spacers (shown in FIG. 2 but not specificallydesignated) and insulative or insulating caps (shown in FIG. 2 but notspecifically designated).

[0020] Conductive lines 20, 22, 24, and 26 constitute a first series ofconductive lines which are formed relative to substrate 12. In theillustrated and preferred embodiment, substrate 12 supports integratedcircuitry which forms memory cells. Even more preferably, such memorycells constitute dynamic random access memory cells. Accordingly, wordline pair 22, 24 share an intervening contact of adjacent pairs ofmemory cells, which in turn share a diffusion region (described below)in substrate 12. Electrical isolation between the adjacent pairs ofmemory cells is provided by intervening conductive isolation lines 20,26 which are formed in conjunction with the formation of word lines 22,24. Lines 20, 26 in operation are connected with ground or a suitablenegative voltage and effectively substitute for the electrical isolationformerly provided by field oxide.

[0021] Referring to FIGS. 1-3, conductive lines 20, 22, 24, and 26 haverespective conductive line tops 21, 23, 25, and 27. Such line tops aredefined by the insulating or insulative caps mentioned above. Aplurality of laterally spaced apart insulated conductive memory cell bitlines 28, 30, and 32 are formed elevationally outwardly of conductivelines 20, 22, 24, and 26 and their respective conductive line tops, andare disposed generally transverse relative to the word lines. Forpurposes of illustration and clarity, the bit lines are indicated inFIG. 1 as a second series of parallel lines at least portions of whichare disposed elevationally over the first series lines 20, 22, 24, and26. In the illustrated and preferred embodiment, individual bit linesare formed elevationally over respective individual isolation oxiderunners 14 as best shown in FIG. 2 for bit line 28 in correspondingextent and shape.

[0022] As formed, the first and second series of conductive linescollectively constitute a plurality of upstanding devices, withindividual conductive word/isolation lines and bit lines constituting agrid of insulated lines which are formed relative to substrate 12.

[0023] Referring to FIGS. 1 and 3, a plurality of node locations 34, 36,and 38 with which electrical connection is desired are defined by thegrid of upstanding devices and between conductive line pairs 20, 22, and22, 24, and 24, 26 which are formed elevationally outwardly thereof.Although only three node locations are shown for purposes ofillustration, other node locations are formed over the array areadefined by substrate 12. In the illustrated and preferred embodiment,node locations 34, 36, and 38 constitute respective diffusion regions40, 42, and 44 which are outwardly exposed. As formed, node locations34, 36, and 38 also constitute first substrate locations which arelaterally surrounded with insulating material. In the illustratedexample, such insulating material constitutes insulative portions offirst series conductive lines 20, 22, 24, and 26, and second seriesconductive bit lines 28, 30, and 32 which are formed elevationallyoutwardly of and generally transverse relative to conductive lines 20,22, 24, and 26. In the illustrated and preferred embodiment, theconductive word/isolation and bit lines are formed to define an adjacentactive area substrate location (corresponding to respective nodelocations 34, 36, and 38) which is laterally surrounded by four of theinsulated conductive lines. In this example, two of such linesconstitute first series lines, and two of such lines constitute secondseries lines.

[0024] In the illustrated example, a mask can and preferably is utilizedto define and expose a plurality of areas 37 (FIG. 1) proximaterespective bit lines 28, 30, and 32. Areas 37 constitute areas whichlaterally expose respective sidewall spacers over the diagrammaticallyillustrated bit lines 28, 30, and 32. Typically, such sidewall spacersare formed from an oxide or nitride material. In a preferred embodiment,the sidewall spacers of conductive lines 20, 22, 24, and 26 comprise anitride material while those of bit lines 28, 30, and 32 comprise anoxide material. The exposed sidewall portions 37 of bit lines 28, 30,and 32 are etched in a wet etch comprising HF at a substantially higherrate than the nitride material sidewalls of conductive lines 20, 22, 24,and 26. Accordingly, such enables contact to be made relative to the bitlines without appreciably etching any inadvertently exposed sidewallmaterial of conductive lines 20, 22, 24, and 26.

[0025] Referring to FIGS. 4 and 5, a fragmentary portion of the FIG. 1substrate is shown. After node locations 34, 36, and 38 are surroundedwith the preferred insulating material and with the bit line conductivesidewall portions being effectively exposed, conductive material 46 isformed or deposited over the grid and the exposed node locations.Exemplary materials for conductive material 46 are polysilicon,tungsten, and the like. Preferably, such conductive material is chemicalvapor deposited to achieve a degree of conformal coverage. Accordingly,conductive material 46 is deposited over the conductive lines and inelectrical connection with the respective node locations as shown inFIG. 5. Conductive material 46 is also preferably in contact with theexposed portions of the bit line sidewalls corresponding to areas 37(FIG. 1), thereby forming an electrical connection with node location36, which, in turn, will form a connection through a word line/gate witha storage node location described below. In the preferred embodiment, adesired amount of conductive material can be less than the height ofadjacent conductive lines, but an amount which is sufficient to fill thespaces between the lines.

[0026] Referring to FIGS. 6 and 7, conductive material 46 is removed toa degree sufficient to form isolated plugs 48, 50, and 52 of conductivematerial (FIG. 6) respectively, over node locations 34, 36, and 38. Plug52 is shown in its cross-sectional entirety in FIG. 7. In theillustrated and preferred embodiment, a photomaskless etch is conductedof conductive material 46 (FIG. 5) to a degree which is sufficient toremove the conductive material from elevationally outward of theinsulating material constituting portions of the conductive lines, andto a degree which is sufficient to leave plugs 48, 50, and 52 overrespective node locations 34, 36, and 38. Accordingly, the photomasklessetch constitutes an etch which is conducted in the absence of anyphotomasking material laterally proximate the node location. Even morepreferably, such etch is conducted in the absence of any photomaskingmaterial over the substrate. The photomaskless etch desirably permitsconductive material to be removed from outside or outwardly of theillustrated array area without the need for a mask in or over the arrayarea. The preferred etching of conductive material 46 constitutes anisotropic etch of the material to a degree sufficient to completelyremove conductive material from over the conductive word/isolationlines, and to expose the insulating material portions of lines 24, 26.Exemplary etches include wet or dry etches, with the latter beingpreferred. Further, exemplary dry etch chemistries can include one ormore of the following: CF₄, SF₆, or NF₃. Accordingly, the conductivematerial constituting plug 52 is preferably recessed to elevationallybelow uppermost surfaces or line tops 25, 27.

[0027] Referring to FIG. 8, a layer 54 is formed over substrate 12.Preferably, layer 54 comprises an insulating or insulative material suchas borophosphosilicate glass which is formed over the substrate. Anexemplary thickness for layer 54 is 0.5 μm to 1.5 μm.

[0028] Referring to FIG. 9, an opening 56 is etched or otherwise formedthrough insulative layer 54 to outwardly expose conductive material ofplug 52 overlying node location 38. Preferably such opening isanisotropically etched to outwardly expose plug 52.

[0029] Referring to FIG. 10, a second, spaced apart substrate location58 is formed elevationally outward of and in electrical contact with thefirst substrate location defined by node location 38. In the illustratedand preferred embodiment, the spaced apart first and second substratelocations constitute part of an integrated circuitry memory cell andsubstrate location 58 constitutes a storage capacitor having a storagenode 60, a dielectric layer 62, and cell plate 64. In the illustratedexample, at least a portion of the storage capacitor is disposedelevationally outwardly, above or over the previously formed bit lines28, 30, and 32 (FIG. 1). Accordingly, such constitutes acapacitor-over-bit-line dynamic random access memory cell. Otherintegrated circuit first and second substrate locations are possible,including ones which are not necessarily associated with the abovedescribed integrated circuit memory cells.

[0030] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming an electrically conductive plug to a nodelocation comprising: providing a node location to which electricalconnection is to be made; laterally surrounding the node location withinsulating material and leaving the node location outwardly exposed;after the surrounding, depositing conductive material over theinsulating material and the exposed node location; and conducting aphotomaskless isotropic etch of the conductive material to a degreesufficient to remove conductive material from elevationally outward ofat least some of the insulating material to outwardly expose the atleast some of the insulating material and to leave a plug of theconductive material over the node location.
 2. The method of claim 1,wherein the node location constitutes part of an integrated circuitrymemory cell and the providing of the node location comprises: formingtwo laterally spaced apart conductive lines; and forming a diffusionregion between the conductive lines, the diffusion region comprising thenode location.
 3. The method of claim 1, comprising providing the nodelocation as part of a dynamic random access memory cell, and wherein thesurrounding of the node location comprises forming insulated bit lineselevationally outwardly of the node location prior to conducting thephotomaskless isotropic etch.
 4. The method of claim 1, comprising:providing the node location as part of a dynamic random access memorycell; wherein the surrounding of the node location comprises forminginsulated bit lines elevationally outwardly of the node location; afterthe forming of the insulated bit lines, conducting the photomasklessisotropic etch; and after the conducting of the photomaskless isotropicetch, forming a memory cell storage capacitor to be in electricalcontact with the plug.
 5. The method of claim 1, wherein the providingof the node location comprises forming a diffusion region within asubstrate as part of an integrated circuitry memory cell and thesurrounding of the node location comprises: forming a grid of conductivelines over the substrate, the grid comprising a) a first series ofconductive lines which are formed over the substrate at least two of theconductive lines constitute conductive word lines, the diffusion regionbeing formed between two laterally spaced apart first series lines, andb) a second series of conductive lines at least some of which constituteconductive bit lines formed elevationally outwardly of and generallytransverse relative to the first series conductive lines, at least someof the diffusion region being outwardly exposed between respectiveindividual first and second series lines.
 6. A method of forming anelectrical connection with an integrated circuitry memory cell nodelocation comprising: forming a plurality of insulated conductive linesover a semiconductive substrate, at least some of the conductive linesextending over a semiconductive substrate active area and constitutingword lines, at least some other of the conductive lines having at leastsome portions disposed elevationally over the word lines andconstituting bit lines, the conductive lines being formed to define anactive area substrate location laterally surrounded by at least four ofsaid insulated conductive lines; depositing conductive material over thesubstrate and the insulated conductive lines and in electrical contactwith the active area substrate location; and with the conductivematerial being outwardly exposed over the active area substrate locationand over the at least four of said insulated conductive lines,isotropically etching the conductive material to a degree sufficient toform an isolated plug over the node location and between the at leastfour of said insulated conductive lines.
 7. The method of forming anelectrical connection of claim 6 further comprising after the etching ofthe conductive material, forming at least one memory cell storagecapacitor to be in electrical contact with said isolated plug.
 8. Themethod of forming an electrical connection of claim 6, wherein theetching of the conductive material comprises etching the conductivematerial to a degree sufficient to expose at least some materialconstituting insulated portions of at least some of the conductivelines.
 9. The method of forming an electrical connection of claim 6,wherein the etching of the conductive material comprises etching theconductive material to a degree sufficient to recess the conductivematerial to elevationally below an insulative portion of an adjacentconductive line.
 10. The method of forming an electrical connection ofclaim 6, wherein the isotropic etching comprises conducting the etchingwith no photoresist overlying any portion of the substrate.
 11. Information of a capacitor-over-bit-line dynamic random access memorycell, a method of making electrical connection to a node locationcomprising: forming a pair of conductive lines over a semiconductivesubstrate, the conductive lines defining a node location therebetweenand relative to an active area on the substrate; depositing conductivematerial over the conductive lines and between the conductive lines inelectrical contact with the node location; isotropically etching theconductive material to a degree sufficient to completely removeconductive material from over the pair of conductive lines and to leavea conductive material plug over the node location; after the isotropicetching, forming an insulative material over the substrate and the nodelocation; and forming an opening through the insulative material tooutwardly expose the conductive material plug.
 12. The method of claim11, wherein the isotropic etching comprises conducting the etching inthe absence of any photomasking material over the substrate active area.13. The method of claim 11, wherein the substrate comprises an arrayarea and a peripheral area, the node location being defined within thearray area, and wherein the isotropic etching comprises conducting theetching in the absence of any photomasking material over the array area.14. The method of claim 11 comprising prior to the isotropic etching,forming memory cell bit lines over the substrate.
 15. The method ofclaim 11 comprising prior to the isotropic etching, forming memory cellbit lines over the substrate and further wherein the isotropic etchingcomprises conducting the etching in the absence of any photomaskingmaterial over the substrate active area.
 16. In formation of acapacitor-over-bit-line dynamic random access memory device, a method ofmaking electrical connection to a node location comprising: forming apair of spaced apart isolation oxide runners received within asemiconductive substrate; forming a pair of conductive lines over thesemiconductive substrate, the conductive lines extending generallytransverse relative to the isolation oxide runners, at least one of theconductive lines constituting a conductive word line; forming a pair ofconductive memory cell bit lines, individual bit lines being disposedelevationally over respective individual isolation oxide runners andgenerally transverse the pair of conductive lines; forming a diffusednode location adjacent the at least one conductive word line; depositingconductive material over the substrate and in electrical contact withthe diffused node location; isotropically etching the conductivematerial to a degree sufficient to completely remove conductive materialfrom over the pair of conductive lines and to leave a conductivematerial plug over the diffused node location; after the isotropicetching, forming an insulative material over the substrate and thediffused node location; and forming an opening through the insulativematerial to outwardly expose the conductive material plug.
 17. Themethod of claim 16, wherein the at least one conductive word line of thepair of conductive lines constitutes a portion of a memory cell, and theforming of the pair of conductive lines comprises forming the other ofthe pair of conductive lines to be a conductive isolation line forproviding electrical isolation relative to an adjacent memory cell. 18.A method of forming an electrical connection between elevationallyspaced apart substrate locations comprising: forming a first substratelocation to which electrical connection is to be made, the firstsubstrate location comprising a diffusion region which is receivedwithin the substrate; forming insulating material to laterally surroundthe first substrate location to a degree sufficient to leave at least aportion of the diffusion region outwardly exposed; depositing conductivematerial over the insulating material and in electrical contact with thefirst substrate location; in the absence of any photomasking materiallaterally proximate the first substrate location, etching the conductivematerial to a degree sufficient to recess the conductive material toelevationally below an uppermost surface of the insulating material andto leave a plug of conductive material over the first substratelocation; forming an insulating layer over the first substrate location;etching a contact opening through the insulating layer to expose atleast a portion of the plug of conductive material; and forming a secondsubstrate location elevationally outward of the first substrate locationand in electrical contact with the plug of conductive material.
 19. Themethod of claim 18, wherein the spaced apart substrate locationsconstitute part of an integrated circuitry memory cell, and the formingof the second substrate location comprises forming a storage capacitor.20. The method of claim 18, wherein the spaced apart substrate locationsconstitute part of an integrated circuitry memory cell, and wherein: theforming of the insulating material to laterally surround the firstsubstrate location comprises forming a plurality of insulated conductivelines outwardly of the first substrate location; and the forming of thesecond substrate location comprises: after forming the plurality ofinsulated conductive lines, forming a storage capacitor at least some ofwhich being disposed elevationally outwardly of the conductive lines.21. The method of claim 18, wherein the spaced apart substrate locationsconstitute part of an integrated circuitry memory cell, and wherein: theforming of the insulating material to laterally surround the firstsubstrate location comprises forming a plurality of insulated conductivelines outwardly of the first substrate location, the plurality ofinsulated conductive lines comprising: a) a first series of conductivelines some of which constitute conductive word lines and others of whichconstitute conductive isolation lines, and b) a second series ofconductive lines disposed elevationally outwardly of and generallytransverse relative to the first series of conductive lines, at leastsome of the second series of conductive lines constitute bit lines; andthe forming of the second substrate location comprises: after formingthe plurality of insulated conductive lines, forming a storage capacitorat least some of which being disposed elevationally outwardly of the bitlines.
 22. The method of claim 18, wherein the etching of the conductivematerial comprises isotropically etching the conductive material.
 23. Amethod of forming an electrically conductive plug to a node locationcomprising: providing a node location to which electrical connection isto be made; laterally surrounding the node location with a plurality ofupstanding devices and leaving the node location outwardly exposed;after the surrounding, depositing conductive material over theupstanding devices and the exposed node location; and with theconductive material being outwardly exposed over the node location andover the plurality of upstanding devices immediately adjacent the nodelocation, isotropically etching the conductive material to a degreesufficient to form an isolated plug over the node location between theupstanding devices.
 24. The method of claim 23, wherein the surroundingof the node location with a plurality of upstanding devices comprisesforming a plurality of insulated conductive lines elevationallyoutwardly of the node location.
 25. The method of claim 23, wherein thesurrounding of the node location with a plurality of upstanding devicesconsists essentially of forming a plurality of insulated conductivelines elevationally outwardly of the node location.
 26. The method ofclaim 23, wherein: the providing of the node location comprises forminga diffusion region within a substrate; and the surrounding of the nodelocation with a plurality of upstanding devices comprises: forming agrid of conductive lines over the substrate, the grid comprising a) afirst series of conductive lines at least some of which constituteconductive word lines, the diffusion region being formed between twolaterally spaced apart first series lines, and b) a second series ofconductive lines at least some of which constitute bit lines formedelevationally outwardly of and generally transverse relative to thefirst series lines.
 27. The method of claim 23, wherein: the providingof the node location comprises forming a diffusion region within asubstrate; and the surrounding of the node location with a plurality ofupstanding devices comprises: forming a grid of conductive lines overthe substrate, the grid comprising a) a first series of conductive linesat least some of which constitute conductive word lines and others ofwhich constitute conductive isolation lines for providing electricalisolation within continuous substrate active area regions formedtherebeneath, the diffusion region being formed between two laterallyspaced apart first series lines, and b) a second series of conductivelines at least some of which constitute bit lines formed elevationallyoutwardly of and generally transverse relative to the first serieslines, the grid comprising a plurality of memory cells.
 28. A method offorming an electrically conductive plug to a node location comprising:forming a plurality of isolation oxide runners within a substrate,respective pairs of runners defining continuous substrate active areastherebetween; forming a first series of insulated conductive lines overthe substrate, individual first series lines being laterally spacedapart relative to one another and disposed generally transverse relativeto the isolation oxide runners, individual first series lines havingrespective line tops comprising insulating material; forming a secondseries of insulated conductive lines over the substrate, individualsecond series lines being laterally spaced apart relative to one anotherand disposed generally transverse the first series lines, wherein thefirst and second series lines constitute a grid which defines at leastone outwardly exposed node location with which electrical connection isto be made, the node location being laterally surrounded with insulatingmaterial which constitutes portions of the grid of first and secondseries lines; depositing conductive material over the grid and theexposed node location; and conducting a photomaskless isotropic etch ofthe conductive material to a degree sufficient to recess the conductivematerial to elevationally below the first series line tops and to leavea plug of conductive material over the node location.
 29. The method ofclaim 28, wherein the forming of the second series of insulatedconductive lines comprises forming at least some individual secondseries lines elevationally over respective isolation oxide runners.